EFM32G-DK3550【PDF 241/467 页】KIT DEVELOPMENT EFM32 GECKO

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...the world's most energy friendly microcontrollers

Bit

4

Name

RXUF

Reset

0

Access

RW

Description

RX Underflow Interrupt Enable

Enable interrupt on RX underflow.

3

RXOF

0

RW

RX Overflow Interrupt Enable

Enable interrupt on RX overflow.

2

RXDATAV

0

RW

RX Data Valid Interrupt Enable

Enable interrupt on RX data.

1

TXBL

0

RW

TX Buffer Level Interrupt Enable

Enable interrupt on TX buffer level.

0

TXC

0

RW

TX Complete Interrupt Enable

Enable interrupt on TX complete.

18.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)

For more information about Asynchronous Registers please see Section 5.3 (p. 18) .

Offset

0x03C

Reset

Access

Name

Bit Position

Bit

Name

Reset

Access

Description

31:6

Reserved

To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)

5

PULSEFILT

0

RW

Pulse Filter

Enable a one-cycle pulse filter for pulse extender

Value

0

1

Description

Filter is disabled. Pulses must be at least 2 cycles long for reliable detection.

Filter is enabled. Pulses must be at least 3 cycles long for reliable detection.

4

PULSEEN

0

RW

Pulse Generator/Extender Enable

Filter LEUART output through pulse generator and the LEUART input through the pulse extender.

3:0

PULSEW

0x0

RW

Pulse Width

Configure the pulse width of the pulse generator as a number of 32.768 kHz clock cycles.

18.5.17 LEUARTn_FREEZE - Freeze Register

Offset

0x040

Reset

Access

Name

Bit Position

2011-04-12 - d0001_Rev1.10

241

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